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Network Clock Generator, Two Outputs AD9575
FEATURES
Fully integrated VCO/PLL core 0.39 ps rms jitter from 12 kHz to 20 MHz at 156.25 MHz 0.15 ps rms jitter from 1.875 MHz to 20 MHz at 156.25 MHz 0.40 ps rms jitter from 12 kHz to 20 MHz at 106.25 MHz 0.15 ps rms jitter from 637 kHz to 10 MHz at 106.25 MHz Input crystal frequency of 19.44 MHz, 25 MHz, or 25.78125 MHz Pin selectable divide ratios for 33.33 MHz, 62.5 MHz, 100 MHz, 106.25 MHz, 125 MHz, 155.52 MHz, 156.25 MHz, 159.375 MHz, 161.13 MHz, and 312.5 MHz outputs LVDS/LVPECL/LVCMOS output format Integrated loop filter Space saving 4.4 mm x 5.0 mm TSSOP 100 mW power dissipation (LVDS output) 120 mW power dissipation (LVPECL output) 3.3 V operation
GENERAL DESCRIPTION
The AD9575 provides a highly integrated, dual output clock generator function including an on-chip PLL core that is optimized for network clocking. The integer-N PLL design is based on the Analog Devices, Inc., proven portfolio of high performance, low jitter frequency synthesizers to maximize line card performance. Other applications with demanding phase noise and jitter requirements also benefit from this part. The PLL section consists of a low noise phase frequency detector (PFD), a precision charge pump, a low phase noise voltage controlled oscillator (VCO), and pin selectable feedback and output dividers. By connecting an external crystal, popular network output frequencies can be locked to the input reference. The output divider and feedback divider ratios are pin programmable for the required output rates. No external loop filter components are required, thus conserving valuable design time and board space. The AD9575 is available in a 16-lead, 4.4 mm x 5.0 mm TSSOP and can be operated from a single 3.3 V supply. The temperature range is -40C to +85C.
APPLICATIONS
GbE/FC/SONET line cards, switches, and routers CPU/PCI-e applications Low jitter, low phase noise clock generation
FUNCTIONAL BLOCK DIAGRAM
VDD x 5 LDO
THIRD-ORDER LPF PFD/CP
LVDS OR LVPECL
DIVIDERS
XTAL OSC
VCO
100MHz TO 312.5MHz LVCMOS 33.33MHz/ 62.5MHz/SEL1 SEL
08462-001
AD9575
GND x 5
SEL0
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2010 Analog Devices, Inc. All rights reserved.
AD9575 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 PLL Characteristics ...................................................................... 3 LVDS Clock Output Jitter (Typ/Max)........................................ 4 LVPECL Clock Output Jitter (Typ/Max)................................... 4 Output Frequency Select ............................................................. 5 Clock Outputs ............................................................................... 5 Timing Characteristics ................................................................ 5 Power .............................................................................................. 6 Crystal Oscillator .......................................................................... 6 Timing Diagrams.......................................................................... 6 Absolute Maximum Ratings ............................................................7 Thermal Resistance .......................................................................7 ESD Caution...................................................................................7 Pin Configuration and Function Descriptions..............................8 Typical Performance Characteristics ..............................................9 Terminology .................................................................................... 11 Theory of Operation ...................................................................... 12 Phase Frequency Detector (PFD) and Charge Pump............ 12 Power Supply............................................................................... 12 LVPECL Clock Distribution ..................................................... 12 LVDS Clock Distribution .......................................................... 13 LVCMOS Clock Distribution ................................................... 13 Typical Applications ................................................................... 13 Outline Dimensions ....................................................................... 14 Ordering Guide .......................................................................... 14
REVISION HISTORY
1/10--Revision 0: Initial Version
Rev. 0 | Page 2 of 16
AD9575 SPECIFICATIONS
Typical (typ) value is given for VDD = 3.3 V 10%, TA = 25C, unless otherwise noted. Minimum (min) and maximum (max) values are given over full VDD and TA (-40C to +85C) variation.
PLL CHARACTERISTICS
Table 1.
Parameter PHASE NOISE CHARACTERISTICS PLL Noise (100 MHz Output) At 1 kHz At 10 kHz At 100 kHz At 1 MHz At 10 MHz At 30 MHz PLL Noise (106.25 MHz Output) At 1 kHz At 10 kHz At 100 kHz At 1 MHz At 10 MHz At 30 MHz PLL Noise (125 MHz Output) At 1 kHz At 10 kHz At 100 kHz At 1 MHz At 10 MHz At 30 MHz PLL Noise (155.52 MHz Output) At 1 kHz At 10 kHz At 100 kHz At 1 MHz At 10 MHz At 30 MHz PLL Noise (156.25 MHz Output) At 1 kHz At 10 kHz At 100 kHz At 1 MHz At 10 MHz At 30 MHz PLL Noise (159.375 MHz Output) At 1 kHz At 10 kHz At 100 kHz At 1 MHz At 10 MHz At 30 MHz Min LVDS Typ Max Min LVCMOS Typ Max Min LVPECL Typ Max Unit
-123 -128 -131 -150 -156 -156 -121 -127 -130 -149 -156 -156 -120 -126 -128 -148 -155 -156 -118 -123 -125 -147 -155 -156 -118 -124 -126 -146 -155 -155 -118 -124 -126 -146 -155 -155
-122 -129 -131 -151 -158 -158 -121 -128 -130 -150 -158 -159 -120 -127 -129 -150 -157 -158 -118 -123 -125 -149 -157 -157 -118 -125 -127 -148 -157 -157 -118 -125 -126 -147 -156 -157
dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz
Rev. 0 | Page 3 of 16
AD9575
Parameter PLL Noise (312.5 MHz Output) At 1 kHz At 10 kHz At 100 kHz At 1 MHz At 10 MHz At 30 MHz PLL Noise (33.33 MHz Output) At 1 kHz At 10 kHz At 100 kHz At 1 MHz At 5 MHz PLL Noise (62.5 MHz Output) At 1 kHz At 10 kHz At 100 kHz At 1 MHz At 5 MHz Spurious Content PLL Figure of Merit Min LVDS Typ -112 -119 -120 -140 -152 -153 -131 -138 -140 -155 -155 -126 -133 -134 -150 -152 -70 -217 -70 -217 Max Min LVCMOS Typ Max Min LVPECL Typ -112 -119 -120 -142 -154 -155 Max Unit dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc dBc/Hz
LVDS CLOCK OUTPUT JITTER (TYP/MAX)
Typical (typ) value is given for VS = 3.3 V, TA = 25C, unless otherwise noted. Table 2.
Jitter Integration Bandwidth 12 kHz to 20 MHz 1.875 MHz to 20 MHz 0.637 MHz to 10 MHz 100 MHz 0.38/0.50 106.25 MHz 0.40/0.54 0.15/0.21 125 MHz 0.37/0.47 155.52 MHz 0.41/0.54 156.25 MHz 0.39/0.51 0.15/0.27 159.375 MHz 0.38/0.51 312.5 MHz 0.36/0.48 Unit ps rms ps rms ps rms
LVPECL CLOCK OUTPUT JITTER (TYP/MAX)
Typical (typ) value is given for VS = 3.3 V, TA = 25C, unless otherwise noted. Table 3.
Jitter Integration Bandwidth 12 kHz to 20 MHz 1.875 MHz to 20 MHz 0.637 MHz to 10 MHz 100 MHz 0.36/0.46 106.25 MHz 0.44/0.68 0.22/0.35 125 MHz 0.36/0.45 155.52 MHz 0.40/0.52 156.25 MHz 0.39/0.64 0.19/0.54 159.375 MHz 0.41/0.62 312.5 MHz 0.38/0.49 Unit ps rms ps rms ps rms
Rev. 0 | Page 4 of 16
AD9575
OUTPUT FREQUENCY SELECT
Typical (typ) value is given for VS = 3.3 V, TA = 25C, unless otherwise noted Table 4.
Parameter Select Pins (SEL0/SEL1) Logic 1 Voltage Logic 0 Voltage Logic 1 Current Logic 0 Current Min 0.83 x VS + 0.2 0.33 x VS - 0.2 190 150 Typ Max Unit V V A A Test Conditions/Comments
Pull-down to GND, pull-up to VDD, pull-up to VDD via 15 k, do not connect
CLOCK OUTPUTS
Typical (typ) value is given for VS = 3.3 V, TA = 25C, unless otherwise noted. Table 5.
Parameter LVDS CLOCK OUTPUT Output Frequency Differential Output Voltage (VOD) Delta VOD Output Offset Voltage (VOS) Delta VOS Short-Circuit Current (ISA, ISB) Duty Cycle LVPECL CLOCK OUTPUT Output Frequency Output High Voltage (VOH) Output Low Voltage (VOL) Differential Output Voltage (VOD) Duty Cycle LVCMOS CLOCK OUTPUT Output Frequency Output High Voltage (VOH) Output Low Voltage (VOL) Duty Cycle Min Typ Max 312.5 450 25 1.375 25 24 55 312.5 VS - 0.8 VS - 1.7 800 55 62.5 VS - 0.1 45 50 0.1 55 Unit MHz mV mV V mV mA % MHz V V mV % MHz V V % Test Conditions/Comments Termination = 100 differential; default Refer to Figure 2 for definition
250 1.125
340 1.25 14 50
Output shorted to GND
45
VS - 1.5 VS - 2.5 430 45
VS -1.05 VS -1.75 640 50
Refer to Figure 2 for definition
TIMING CHARACTERISTICS
Table 6.
Parameter LVDS Output Rise Time, tRL Output Fall Time, tFL LVPECL Output Rise Time, tRL Output Fall Time, tFL LVCMOS Output Rise Time, tRC Output Fall Time, tFC Min 150 150 180 180 0.50 0.50 Typ 200 200 250 250 0.70 0.70 Max 300 300 300 300 1.10 1.10 Unit ps ps ps ps ns ns Test Conditions/Comments Termination = 100 differential; CLOAD = 0 pF 20% to 80%, measured differentially 80% to 20%, measured differentially Termination = 200 differential; CLOAD = 0 pF 20% to 80%, measured differentially 80% to 20%, measured differentially Termination = 50 to 0 V; CLOAD = 5 pF 20% to 80%; CLOAD = 5 pF 80% to 20%; CLOAD = 5 pF
Rev. 0 | Page 5 of 16
AD9575
POWER
Table 7.
Parameter POWER SUPPLY POWER DISSIPATION LVDS LVPECL Min 3.0 Typ 3.3 100 120 Max 3.6 130 160 Unit V mW mW
CRYSTAL OSCILLATOR
Table 8.
Parameter CRYSTAL SPECIFICATION Frequency ESR Load Capacitance Phase Noise Stability Min 19.44 Typ 25 18 -138 -30 +30 Max 25.78125 40 Unit MHz pF dBc/Hz ppm Test Conditions/Comments Parallel resonant/fundamental mode
At 1 kHz offset
TIMING DIAGRAMS
DIFFERENTIAL SIGNAL 80% 50% 20%
08462-003
SINGLE-ENDED 80% LVCMOS 5pF LOAD 20%
VOD
tRL
tFL
tRC
tFC
Figure 2. LVDS or LVPECL, Timing and Differential Amplitude
Figure 3. LVCMOS Timing
Rev. 0 | Page 6 of 16
08462-004
AD9575 ABSOLUTE MAXIMUM RATINGS
Table 9.
Parameter VDD, VDDA, VDDX, VDD_CMOS to GND XO1, XO2 to GND LVDS/LVPECL OUT, LVDS/LVPECL OUT, CMOS OUT/SEL1 to GND Junction Temperature1 Storage Temperature Range Lead Temperature (10 sec)
1
THERMAL RESISTANCE
Rating -0.3 V to +3.6 V -0.3 V to VS + 0.3 V -0.3 V to VS + 0.3 V 150C -65C to +150C 300C
JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 10. Thermal Resistance1
Package Type 16-Lead TSSOP
1
JA 90.3
Unit C/W
Thermal impedance measurements were taken on a 4-layer board in still air in accordance with EIA/JESD51-7.
See Table 10 for JA.
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Rev. 0 | Page 7 of 16
AD9575 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
GNDA VDDA VDDX XO1 XO2 GNDX GNDA VDDA
1 2 3 4 5 6 7 8 16 SEL0 15 GND 14 LVDS/LVPECL OUT
AD9575
TOP VIEW (Not to Scale)
13 LVDS/LVPECL OUT 12 VDD 11 VDD_CMOS 10 CMOS OUT/SEL1 9
GND_CMOS
Figure 4. Pin Configuration
Table 11. Pin Function Descriptions
Pin No. 1, 7 2, 8 3 4, 5 6 9 10 11 12 13 14 15 16 Mnemonic GNDA VDDA VDDX XO1, XO2 GNDX GND_CMOS CMOS OUT/SEL1 VDD_CMOS VDD LVDS/LVPECL OUT LVDS/LVPECL OUT GND SEL0 Description Analog Ground. Analog Power Supply (3.3 V). Crystal Oscillator Power Supply. External Crystal. Crystal Oscillator Ground. Ground for LVCMOS Output. LVCMOS Output/Output Frequency Select. Power Supply for LVCMOS Output. Power Supply for LVDS or LVPECL Output. Complementary LVDS or LVPECL Output. LVDS or LVPECL Output. Ground for LVDS or LVPECL Output. Output Frequency Select.
Table 12. Output Frequency Selection1
Mode 1 2 3 4 5 6 7 8
1 2
XTAL 25 MHz 25 MHz 25.78125 MHz 25 MHz 25 MHz 25 MHz 25 MHz 19.44 MHz
SEL0 GND VDD VDD NC 15 k pull-up 15 k pull-up VDD VDD
SEL1 X2 GND GND X2 VDD GND VDD No connect
08462-005
LVDS/LVPECL Output 100 MHz 156.25 MHz 161.132812 MHz 125 MHz 159.375 MHz 312.5 MHz 106.25 MHz 155.52 MHz
LVCMOS Output 33.33 MHz High-Z High-Z 62.5 MHz High-Z High-Z High-Z High-Z
The AD9575 must be power-cycled if the select pin voltages are altered. X = in Mode 1 and Mode 4, Pin 10 is configured as a LVCMOS output by forcing Pin16 to GND.
Rev. 0 | Page 8 of 16
AD9575 TYPICAL PERFORMANCE CHARACTERISTICS
-110 -115 -120 PHASE NOISE (dBc/Hz) -125 -130 -135 -140 -145 -150 -155
08462-006
-110 -115 -120
PHASE NOISE (dBc/Hz)
-125 -130 -135 -140 -145 -150 -155
10k
100k
1M
10M
100M
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 5. Phase Noise at LVPECL, 100 MHz Clock Output
-110 -115 -120
Figure 8. Phase Noise at LVPECL, 155.52 MHz Clock Output
-110 -115 -120
PHASE NOISE (dBc/Hz)
PHASE NOISE (dBc/Hz)
-125 -130 -135 -140 -145 -150 -155
08462-007
-125 -130 -135 -140 -145 -150 -155
10k
100k
1M
10M
100M
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 6. Phase Noise at LVPECL, 106.25 MHz Clock Output
-110 -115 -120
PHASE NOISE (dBc/Hz)
Figure 9. Phase Noise at LVPECL, 156.25 MHz Clock Output
-110 -115 -120
PHASE NOISE (dBc/Hz)
-125 -130 -135 -140 -145 -150 -155
10k 100k 1M 10M 100M
08462-008
-125 -130 -135 -140 -145 -150 -155 10k 100k 1M 10M 100M
08462-011
-160 1k
-160 1k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 7. Phase Noise at LVPECL, 125 MHz Clock Output
Figure 10. Phase Noise at LVPECL, 159.375 MHz Clock Output
Rev. 0 | Page 9 of 16
08462-010
-160 1k
-160 1k
08462-009
-160 1k
-160 1k
AD9575
-110 -115 -120
PHASE NOISE (dBc/Hz)
-125 -130 -135 -140 -145 -150 -155 10k 100k 1M 10M 100M
08462-012
M2
-160 1k
M2 100mV 1ns M3 100mV 1ns
FREQUENCY (Hz)
Figure 11. Phase Noise at LVPECL, 312.5 MHz Clock Output
140
Figure 14. 312.5 MHz LVPECL Output
130 LVDS POWER 120 POWER (mV)
M2
110 LVPECL POWER
100
90
1
2
3
4 MODE
5
6
7
8
08462-021
80
M2 100mV 10ns M3 100mV 10ns
Figure 12. Typical Power Dissipation vs. Mode
Figure 15. 62.5 MHz LVCMOS Output
M2
M2 50mV 2ns M3 50mV 2ns
Figure 13. 156.25 MHz LVDS Output
08462-022
Rev. 0 | Page 10 of 16
08462-024
08462-023
AD9575 TERMINOLOGY
Phase Jitter An ideal sine wave can be thought of as having a continuous and even progression of phase with time from 0 to 360 for each cycle. Actual signals, however, display a certain amount of variation from ideal phase progression over time. This phenomenon is called phase jitter. Although many causes can contribute to phase jitter, one major cause is random noise, which is characterized statistically as Gaussian (normal) in distribution. This phase jitter leads to a spreading out of the energy of the sine wave in the frequency domain, producing a continuous power spectrum. This power spectrum is usually reported as a series of values whose units are dBc/Hz at a given offset in frequency from the sine wave (carrier). The value is a ratio (expressed in dB) of the power contained within a 1 Hz bandwidth with respect to the power at the carrier frequency. For each measurement, the offset from the carrier frequency is also given. Phase Noise It is meaningful to integrate the total power contained within some interval of offset frequencies (for example, 10 kHz to 10 MHz). This is called the integrated phase noise over that frequency offset interval and can be readily related to the time jitter due to the phase noise within that offset frequency interval. Phase noise has a detrimental effect on error rate performance by increasing eye closure at the transmitter output and reducing the jitter tolerance/sensitivity of the receiver. Time Jitter Phase noise is a frequency domain phenomenon. In the time domain, the same effect is exhibited as time jitter. When observing a sine wave, the time of successive zero crossings is seen to vary. In a square wave, the time jitter is seen as a displacement of the edges from their ideal (regular) times of occurrence. In both cases, the variations in timing from the ideal are the time jitter. Because these variations are random in nature, the time jitter is specified in units of seconds root mean square (rms) or 1 sigma of the Gaussian distribution. Additive Phase Noise Additive phase noise is the amount of phase noise that is attributable to the device or subsystem being measured. The phase noise of any external oscillators or clock sources has been subtracted. This makes it possible to predict the degree to which the device impacts the total system phase noise when used in conjunction with the various oscillators and clock sources, each of which contributes its own phase noise to the total. In many cases, the phase noise of one element dominates the system phase noise. Additive Time Jitter Additive time jitter is the amount of time jitter that is attributable to the device or subsystem being measured. The time jitter of any external oscillators or clock sources has been subtracted. This makes it possible to predict the degree to which the device impacts the total system time jitter when used in conjunction with the various oscillators and clock sources, each of which contributes its own time jitter to the total. In many cases, the time jitter of the external oscillators and clock sources dominates the system time jitter.
Rev. 0 | Page 11 of 16
AD9575 THEORY OF OPERATION
VDDA GNDA VDDA GNDA VDD_CMOS GND_CMOS XTAL OSC PHASE FREQUENCY DETECTOR LDO CHARGE PUMP 2.5GHz TO 2.55GHz VCO LVCMOS 1/n 1/k SEL 1/m LVDS 100MHz
08462-015
CMOS OUT/SEL1 SEL0 LVDS/LVPECL OUT LVDS/LVPECL OUT
AD9575
VLDO
Figure 16. Detailed Block Diagram
Figure 16 shows a block diagram of the AD9575. The chip features a PLL core, which is configured to generate the specific clock frequencies via pin programming. By appropriate connection of the select pins, SEL0 and SEL1, as described in Table 12, the divide ratios of the feedback divider (n), LVDS output divider (m), and LVCMOS output divider (k) can be programmed. In Mode 1 and Mode 4, Pin 10 is configured as a LVCMOS output by forcing Pin 16 to GND. In conjunction with a bandselect VCO that operates over the range of 2.488 GHz to 2.55 GHz, a wide range of popular network reference frequencies can be generated. This PLL is based on proven Analog Devices synthesizer technology, noted for its exceptional phase noise performance. The AD9575 is highly integrated and includes the loop filter, a regulator for supply noise immunity, all the necessary dividers, output buffers, and a crystal oscillator. A user need only supply an external crystal to implement a clocking solution, which does not require any processor intervention.
POWER SUPPLY
The AD9575 requires a 3.3 V 10% power supply for VDD. The Specifications section gives the performance expected from the AD9575 with the power supply voltage within this range. The absolute maximum range of -0.3 V to +3.6 V, with respect to GND, must never be exceeded on the VDDX, VDD_CMOS, and VDDA pins. Good engineering practice should be followed in the layout of power supply traces and the ground plane of the PCB. The power supply should be bypassed on the PCB with adequate capacitance (>10 F). The AD9575 should be bypassed with adequate capacitors (0.1 F) at all power pins as close as possible to the part. The layout of the AD9575 evaluation board is a good example.
LVPECL CLOCK DISTRIBUTION
The LVPECL outputs (because they are open emitter) require a dc termination to bias the output transistors. The simplified equivalent circuit in Figure 19 shows the LVPECL output stage. In most applications, a standard LVPECL far-end termination is recommended, as shown in Figure 18. The resistor network is designed to match the transmission line impedance (50 ) and the desired switching threshold (1.3 V).
3.3V 3.3V 3.3V
PHASE FREQUENCY DETECTOR (PFD) AND CHARGE PUMP
The PFD takes inputs from the reference clock and feedback divider to produce an output proportional to the phase and frequency difference between them. Figure 17 shows a simplified schematic.
VP CHARGE PUMP
50 SINGLE-ENDED (NOT COUPLED) 50
127
127
HIGH REFCLK
D1 Q1 CLR1
UP
LVPECL
LVPECL
CP
Figure 18. LVPECL Far-End Termination
HIGH FEEDBACK DIVIDER GND CLR2 DOWN D2 Q2
Figure 17. PFD Simplified Schematic and Timing (in Lock)
08462-016
Rev. 0 | Page 12 of 16
08462-025
VT = VDD - 1.3V
83
83
AD9575
3.3V 0.1nF DIFFERENTIAL 100 (COUPLED) 3.3V
LVPECL
0.1nF 200
LVPECL
200
Figure 19. LVPECL with Parallel Transmission Line
LVDS CLOCK DISTRIBUTION
The AD9575 is also available with low voltage differential signaling (LVDS) outputs. LVDS uses a current mode output stage with a factory programmed current level. The normal value (default) for this current is 3.5 mA, which yields a 350 mV output swing across a 100 resistor. The LVDS outputs meet or exceed all ANSI/TIA/EIA-644 specifications. A recommended termination circuit for the LVDS outputs is shown in Figure 20.
50
08462-017
mismatched impedances on the net. Series termination at the source is generally required to provide transmission line matching and/or to reduce current transients at the driver (see Figure 21). The value of the resistor is dependent on the board design and timing requirements (typically 10 to 100 is used). LVCMOS outputs are limited in terms of the capacitive load or trace length that they can drive. Typically, trace lengths less than 6 inches are recommended to preserve signal rise/fall times and preserve signal integrity.
CMOS 10 60.4 1.0 INCH MICROSTRIP
08462-018
08462-026
5pF GND
Figure 21. Series Termination of LVCMOS Output
LVDS 50
100
LVDS
Termination at the far end of the PCB trace is a second option. The LVCMOS output of the AD9575 does not supply enough current to provide a full voltage swing with a low impedance resistive, far-end termination, as shown in Figure 22. The far-end termination network should match the PCB trace impedance and provide the desired switching point. The reduced signal swing may still meet receiver input requirements in some applications. This can be useful when driving long trace lengths on less critical nets.
VPULLUP = 3.3V 50 100 100 3pF
08462-019
Figure 20. LVDS Output Termination
See the AN-586 Application Note on the Analog Devices website at www.analog.com for more information about LVDS.
LVCMOS CLOCK DISTRIBUTION
The AD9575 provides a 33.33 or 62.5 MHz clock output, which is a dedicated LVCMOS level. Whenever single-ended LVCMOS clocking is used, some of the following general guidelines should be followed. Point-to-point nets should be designed such that a driver has one receiver only on the net, if possible. This allows for simple termination schemes and minimizes ringing due to possible
LVCMOS 10
Figure 22. LVCMOS Output with Far-End Termination
TYPICAL APPLICATIONS
AD9575
1 0.1F VS VS Cx 4 0.1F 5 Cx 6 7 VS 0.1F 8 XO2 GNDX GNDA VDDA 1nF 2 3 VDDA GND 15 14 0.1F XO1 LVDS/LVPECL OUT 13 50 VS VS 0.1F
08462-002
GNDA
SEL0 16
VDDX LVDS/LVPECL OUT
50
RT = 100
VDD 12 VDD_CMOS 11
CMOS OUT/SEL1 10 GND CMOS 9
Figure 23. Typical Application (in LVDS configuration)
Rev. 0 | Page 13 of 16
AD9575 OUTLINE DIMENSIONS
5.10 5.00 4.90
16 9
4.50 4.40 4.30
1 8
6.40 BSC
PIN 1 0.15 0.05 0.65 BSC 0.30 0.19 COPLANARITY 0.10 1.20 MAX
0.20 0.09
SEATING PLANE
8 0
0.75 0.60 0.45
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 24. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters
ORDERING GUIDE
Model1 AD9575ARUZLVD AD9575ARUZPEC AD9575-EVALZ-LVD AD9575-EVALZ-PEC
1
Temperature Range -40C to +85C -40C to +85C
Package Description 16-Lead Thin Shrink Small Outline Package (TSSOP), 96 pcs per Tube, LVDS Output Format 16-Lead Thin Shrink Small Outline Package (TSSOP), 96 pcs per Tube, LVPECL Output Format LVDS Outputs, Evaluation Board LVPECL Outputs, Evaluation Board
Package Option RU-16 RU-16
Z = RoHS Compliant Part.
Rev. 0 | Page 14 of 16
AD9575 NOTES
Rev. 0 | Page 15 of 16
AD9575 NOTES
(c)2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08462-0-1/10(0)
Rev. 0 | Page 16 of 16

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